A dynamic algorithm to reduce power consumption in multi-core processors

Author

Ravichandran, Rahul ; Muralidharan, Vignesh

Author_Institution

Dept. of Electr. & Electron. Eng., SSN Coll. of Eng., Chennai, India

fYear

2015

fDate

19-20 March 2015

Firstpage

1

Lastpage

6

Abstract

The usage of multi-core processors has increased exponentially in the past decade. The need of the hour is to optimize the power and performance of a chip multi-core processor (CMP). In this paper, we propose a dynamic algorithm to improve power efficiency of a CMP using pipeline stage unification (PSU) and dynamic voltage frequency scaling (DVFS). The proposed algorithm alters various parameters like clock frequency, supply voltage, number of active cores, etc dynamically to obtain the best power-performance ratio.

Keywords

low-power electronics; microprocessor chips; multiprocessing systems; DVFS; PSU; chip multicore processor; dynamic algorithm; dynamic voltage frequency scaling; pipeline stage unification; power consumption; power efficiency; Clocks; Heuristic algorithms; Multicore processing; Pipeline processing; Pipelines; Power control; Power demand; chip multi-core processor; dynamic voltage frequency scaling; pipeline stage unification; power-efficiency;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuit, Power and Computing Technologies (ICCPCT), 2015 International Conference on

Conference_Location

Nagercoil

Type

conf

DOI

10.1109/ICCPCT.2015.7159527

Filename

7159527