DocumentCode :
723071
Title :
High precision alignment process for future 3D wafer bonding
Author :
Sugaya, Isao ; Mitsuishi, Hajime ; Maeda, Hidehiro ; Okada, Masashi ; Okamoto, Kazuya
Author_Institution :
Nikon Corp., Yokohama, Japan
fYear :
2015
fDate :
26-29 May 2015
Firstpage :
348
Lastpage :
353
Abstract :
A new precision alignment process suitable for bonding distorted CMOS wafers is proposed. This process includes the following critical procedures: (A) correction of distorted wafers, (B) enhanced global alignment (EGA) for wafer-to-wafer (W2W) bonding, (C) contact between wafers with high alignment accuracy, and (D) clamping to maintain pre-bonding accuracy. The alignment capability was measured by our newly developed IR metrology tool. We obtained an alignment capability of better than 100 nm both theoretically and experimentally.
Keywords :
CMOS integrated circuits; three-dimensional integrated circuits; wafer bonding; 3D wafer bonding; EGA; IR metrology tool; W2W bonding; bonding distorted CMOS wafer; complementary metal oxide semiconductor; distorted wafer correction; enhanced global alignment; high precision alignment process; wafer-to-wafer bonding; Accuracy; Bonding; Clamps; Distortion measurement; Metrology; Pollution measurement; Temperature measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location :
San Diego, CA
Type :
conf
DOI :
10.1109/ECTC.2015.7159616
Filename :
7159616
Link To Document :
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