DocumentCode
723160
Title
Demonstration of 2µm RDL wiring using dry film photoresists and 5µm RDL via by projection lithography for low-cost 2.5D panel-based glass and organic interposers
Author
Furuya, Ryuta ; Hao Lu ; Fuhan Liu ; Hai Deng ; Ando, Tomoyuki ; Sundaram, Venky ; Tummala, Rao
Author_Institution
Ushio Inc., Yokohama, Japan
fYear
2015
fDate
26-29 May 2015
Firstpage
1488
Lastpage
1493
Abstract
High-density packages and 2.5D interposers require 2μm trace widths and gaps, and less than 10μm ultra-small microvias to achieve 20-40μm I/O pitch interconnections. Silicon interposers with through-silicon-vias (TSVs) have been used for such ultra-high density interconnections between logic and memory chips with sub-micron multi-layer copper wiring. However, the high cost of silicon interposers coming from back end of line (BEOL) processes have limited their applicability to mobile systems like smart phones and wearables. Glass and organic interposers have been investigated as a lower cost solution coming from large panel processes and dry film lithography for semi-additive copper metallization. However, achieving high wiring density with low-cost package substrate processes remains a challenge. This paper presents the first demonstration of high resolution photo-lithography processes to achieve 2μm copper line widths and 5-10μm microvias with panel-based processes using newly developed large field projection lithography tools and advanced dry film photoresists. A two-metal layer redistribution layer (RDL) structure integrating 2μm line and space wiring and less than 10μm ultra-small microvias was demonstrated on ultra-thin glass and organic substrates.
Keywords
copper; photoresists; silicon; three-dimensional integrated circuits; vias; 25D panel-based glass interposers; BEOL processes; Cu; RDL structure; RDL wiring; Si; back end of line processes; copper line widths; dry film photoresists; microvias; organic interposers; panel-based processes; photolithography processes; projection lithography; redistribution layer; silicon interposers; size 2 mum; size 20 mum to 40 mum; size 5 mum to 10 mum; through-silicon-vias; Copper; Films; Glass; Lithography; Resists; Substrates; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
Conference_Location
San Diego, CA
Type
conf
DOI
10.1109/ECTC.2015.7159794
Filename
7159794
Link To Document