Optimization and challenges of backside via flatness reveal process

Through silicon via (TSV) is one of the key technologies in 2.5D and 3D electronic package. When the different materials and processes are used in TSV structure, the warpage, via depth variation and silicon TTV are challenges on backside via reveal process. In this paper, we use backside via flatness reveal process (named as BFR). The process steps include: carrier bond, wafer grinding to via surface exposed, silicon and via surface polishing by CMP, wet etching to reveal Cu nails, etching post-cleaning, passivation deposition with PECVD, and 2nd via reveal by CMP. We discuss the challenges and optimization ways in this paper, including: (1) eliminate de-lamination issue in adhesion layer by added protection layer, (2) to optimize wafer thinning and CMP polishing to reduce the saw marks that enhance by etching process, (3) silicon wet etching by hydroxide base chemical that silicon surface is smoothness, via footing and etching rate could be control by different temperature and chemical proportion, and (4) after the post cleaning, there is no silica residual and copper contamination around via. The BFR process can work on high warpage or large TTV product without worried about via depth variation.