A fracture mechanics based parametric study with dimensional variables of the Cu-Cu direct thermo-Compression bonded interface using FEA

Through-silicon via (TSV) technology with micro joint has been highlighted to overcome the limitations of I/O density and system performance enhancement of the conventional flip chip packages. However, the conventional joining methods, represented by the solder joint, cause many reliability problems, such as: intermetallic compound (IMC), thermal expansion coefficient (CTE) mismatch, creep and thermal fatigue problems. As an alternative, copper-to-copper direct bonding (CuDB) has been considered, especially located between a chip and an interposer as a substitute for the micro bump. CuDB enables reduction in fabrication process steps, and obtaining higher interconnect density and enhanced thermal conductivity. However, the CuDB interface has potential reliability risk since the bonding is typically performed at high temperature with a constant downward force in an inert atmosphere. Several papers have reported small voids between the interfaces that can lead crack propagation and delamination. The defect can result in fracture failure of an entire package during its fabrications and operation. This work is a quantitative parametric study about crack propagation at the CuDB interface using finite element methods (FEM). A pre-crack is assigned at the interface of the CuDB to reflect a small void which can be formed during the thermal compressive bonding process. Initial crack length and location, Cu bump diameter and pitch, and TSV diameter and pitch are varied to determine their impact on the crack propagation of the CuDB. As a computational domain, a unit cell including the outermost C4 solder ball, which is under the maximum warpage, is chosen. The unit cell consists of an intermediate layer, two silicon tiers, and a Cu microbump connected to a TSV with total 20 um width and 108 um height. The strain energy release rate (ERR) around the crack tip is calculated for a quantitative assessment. The results are verified with the J-integral method. As results, this stud- provides design recommendations that can minimize interfacial failure of the CuDB and modeling method, which can be used for efficient prediction of its failure possibility.