• DocumentCode
    723225
  • Title

    Wideband 40GHz TSV modeling analysis under high speed on double side probing methodology

  • Author

    Chiu Hsiang Wang ; Kuang-Chin Fan ; Hsin-Hung Lee

  • Author_Institution
    Adv. Product Design & Testing Dept, Siliconware Precision Ind. Co., Ltd., Taichung, Taiwan
  • fYear
    2015
  • fDate
    26-29 May 2015
  • Firstpage
    2026
  • Lastpage
    2029
  • Abstract
    The Wide bandwidth and smaller form factor, high-speed TSV I/O channel design in three-dimensional integrated circuit (3D IC) becomes a trend with the unremittingly evolving technology, Through-silicon-Via (TSV) provide low power consumption and miniature chip size base on reduction of the vertical interconnection between stacked dies. However this TSV based 3D-IC systems is a significant design consideration is the coupling noise between aggressor and victim TSV. There are many high speed I/O signal integration issues in 3D IC DDR memory, so crosstalk propagation through silicon via is a serious limiting factor on the performance of 3D IC devices and circuits. This paper discusses factors jitter affecting crosstalk which distance between aggressor and victim TSV and ranging it from 20μm, 60μm, 100μm to 200μm, we also design some fence ground pattern to isolation crosstalk effect between aggressor and victim TSV. That has been made to verify the Radio-Frequency (RF) characteristic of double side four ports TSV. We propose the modified high speed electrical equivalent model of TSV with several shielded TSV on ground. This model circuit helps to understand the measurement and simulation of accuracy on high speed I/O and find DDR signal issue in eye diagram analysis. Therefore, the measurement will be absolutely precise with the embedded way on measurement. With the help of the direct double side probing system, four ports S parameters were measured up to 40 GHz to validate the modeled results.
  • Keywords
    S-parameters; crosstalk; high-speed integrated circuits; integrated circuit interconnections; jitter; power consumption; submillimetre wave integrated circuits; three-dimensional integrated circuits; 3D IC DDR memory; RF characteristic; coupling noise; double side probing methodology; eye diagram analysis; fence ground pattern; form factor; four ports S-parameters; frequency 40 GHz; high speed I/O signal integration; high speed electrical equivalent model; high-speed TSV I/O channel design; isolation crosstalk propagation; jitter; miniature chip size; power consumption; radiofrequency characteristic; size 20 mum to 200 mum; stacked dies; three-dimensional integrated circuit; through-silicon-via; vertical interconnection reduction; wideband TSV modeling analysis; Analytical models; Couplings; Crosstalk; Integrated circuit modeling; Radio frequency; Silicon; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC) , 2015 IEEE 65th
  • Conference_Location
    San Diego, CA
  • Type

    conf

  • DOI
    10.1109/ECTC.2015.7159880
  • Filename
    7159880