DocumentCode
723282
Title
Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS
Author
Junyi Liu ; Bayliss, Samuel ; Constantinides, George A.
Author_Institution
Dept. of Electr. & Electron. Eng., Imperial Coll. London, London, UK
fYear
2015
fDate
2-6 May 2015
Firstpage
159
Lastpage
162
Abstract
Loop pipelining is probably the most important optimization method in high-level synthesis (HLS), allowing multiple loop iterations to execute in a pipeline. In this paper, we extend the capability of loop pipelining in HLS to handle loops with uncertain memory behaviours. We extend polyhedral synthesis techniques to the parametric case, offloading the uncertainty to parameter values determined at run time. Our technique then synthesizes lightweight runtime checks to detect the case where a low initiation interval (II) is achievable, resulting in a run-time switch between aggressive (fast) and conservative (slow) execution modes. This optimization is implemented into an automated source-to-source code transformation framework with Xilinx Vivado HLS as one RTL generation backend. Over a suite of benchmarks, experiments show that our optimization can implement transformed pipelines at almost same clock frequency as that generated directly with Vivado HLS, but with approximately 10× faster initiation interval in the fast case, while consuming approximately 60% more resource.
Keywords
circuit optimisation; field programmable gate arrays; high level synthesis; logic design; logic testing; source code (software); High-level synthesis; RTL generation backend; Xilinx Vivado HLS; aggressive execution modes; automated source-to-source code transformation framework; clock frequency; conservative execution modes; high-level synthesis; multiple loop iterations; offline synthesis; online dependence testing; optimization method; parametric loop pipelining; polyhedral synthesis techniques; run-time switch; uncertain memory behaviours; Arrays; Benchmark testing; Field programmable gate arrays; Optimization; Pipeline processing; Pipelines; Runtime; FPGA; High-level Synthesis; Loop Pipelining; Polyhedral Analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Field-Programmable Custom Computing Machines (FCCM), 2015 IEEE 23rd Annual International Symposium on
Conference_Location
Vancouver, BC
Type
conf
DOI
10.1109/FCCM.2015.31
Filename
7160061
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