Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System

High Performance Embedded Computing (HPEC) applications are becoming highly sophisticated as they capture and process real-time data from several sources. In addition, they should adapt their functionalities according to the operational environments. The inherent hardware parallelism that allows Single Program Multiple Data (SPMD) execution model, high-speed serial I/O and Dynamic Partial Reconfiguration (DPR) features make FPGAs a highly attractive solution. The problem with current generation reconfigurable HPEC systems is that, they are usually built to meet the needs of a specific application i.e., Lacks flexibility to upgrade hardware resources or adaptability to different applications. In order to address these challenges, we propose a scalable and modular multi-FPGA computing platform, with a parallel full-duplex customizable communication network, that redefines the computation, communication and reconfiguration paradigms in such applications. Furthermore, in order to adapt to real-time application constraints, we propose a parallel DPR model. It is well-traced on the execution model (SPMD), to reconfigure all or a subset of the computing nodes in parallel during runtime.