Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area

Integrating reconfigurable fabrics in SOCs require an accurate estimation of the layout area of the reconfigurable fabrics in order to properly accommodate early floor-planning. This work examines the accuracy of using minimum width transistor area, a widely used area model in many previous FPGA architectural studies, in assisting floor-planning process. In particular, the layout areas of LUT multiplexers are used as a case study. We found that comparing to the minimum width transistor area, the traditional metal area based stick diagrams can provide much more accurate layout area estimations. In particular, minimum width transistor area can underestimate the layout area of LUT multiplexers by as much as a factor of 3-4 while stick diagrams can achieve over 80 percent accuracy in layout area estimation.