DocumentCode :
72464
Title :
Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking
Author :
Plaza, Stephen M. ; Markov, Igor L.
Author_Institution :
Janelia Res. Campus, Ashburn, VA, USA
Volume :
34
Issue :
6
fYear :
2015
fDate :
Jun-15
Firstpage :
961
Lastpage :
971
Abstract :
The increasing IC manufacturing cost encourages a business model where design houses outsource IC fabrication to remote foundries. Despite cost savings, this model exposes design houses to IC piracy as remote foundries can manufacture in excess to sell on the black market. Recent efforts in digital hardware security aim to thwart piracy by using XOR-based chip locking, cryptography, and active metering. To counter direct attacks and lower the exposure of unlocked circuits to the foundry, we introduce a multiplexor-based locking strategy that preserves test response allowing IC testing by an untrusted party before activation. We demonstrate a simple yet effective attack against a locked circuit that does not preserve test response, and validate the effectiveness of our locking strategy on IWLS 2005 benchmarks.
Keywords :
integrated circuit manufacture; integrated circuit modelling; logic design; logic testing; IC manufacturing cost; IC piracy; IWLS 2005 benchmarks; XOR-based chip locking; active metering; business model; cost savings; counter direct attacks; cryptography; design houses outsource IC fabrication; digital hardware security; remote foundries; test-aware logic locking; third-shift problem; thwart piracy; Cryptography; Fabrication; Integrated circuit modeling; Logic gates; Tin; Vectors; Chip locking; EPIC; IP protection; chip locking; design for testability; ending piracy of integrated circuits (EPIC); secure hardware; third-shift problem;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2015.2404876
Filename :
7045595
Link To Document :
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