Analyses of phase noise reduction techniques in CMOS Hartley oscillator topology at the mm-waves: Inductive degeneration and optimum current density

This paper reports the analyses of two techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. Namely, the two techniques inductive degeneration and optimum current density are investigated with the objective of exploring the potential benefits in the mm-waves frequency range. The circuit sizing is carried out in 28 nm bulk CMOS technology. Overall, the analyses show that the adoption of these techniques may lead to a potential phase noise reduction up to 6 dB at a 1 MHz frequency offset for an oscillation frequency of 100 GHz.