Digital post-correction of analog-to-digital converters with real-time FPGA implementation

In this paper, a novel digital post-correction method with real-time FPGA implementation is proposed to correct the distortion generated by high-speed analog-to-digital converters (ADCs). It is achieved by simplifying the dynamic deviation reduction-based Volterra series to form an accurate model to effectively compensate both static nonlinearities and memory effects. Both post-correction model generation and model extraction modules can be readily implemented in FPGA, which provides great flexibilities in realizing real-time calibration. Experimental results demonstrated that excellent calibration performance can be achieved with very low implementation complexity by employing the proposed method.