DocumentCode
725097
Title
Yield improvement in 2x node technology by introducing backside cleaning
Author
Garg, Niti ; Rajagopalan, Balajee ; Scott, Silas ; Hoech, Raita
Author_Institution
GLOBALFOUNDRIES Inc., Malta, NY, USA
fYear
2015
fDate
3-6 May 2015
Firstpage
379
Lastpage
383
Abstract
Advanced technology nodes require low defects counts at every processing step. Wafer cleaning of the backside is a neglected area. During HVM (high volume manufacturing) for 2x nm nodes we found that cleaning the backside (BS) of the wafer have dramatic improvements in defectivity reduction and yield increase. During HVM of 2x node, defects from BS of wafer were found to fall on the wafer underneath while in the FOUP (Front Opening Unified Pod), specifically in BEOL processing. This contamination fell on the device side/ front side (FS) of the wafer surface and resulted in missing pattern, blocked plating, line voids and surface defects. In this paper, we present the impact of BS cleans on defectivity reduction, and on downstream process resulting in significant yield increase for 2x node HVM.
Keywords
integrated circuit yield; semiconductor technology; surface cleaning; 2x nm nodes; 2x node technology; BEOL processing; FOUP; HVM; backside cleaning; blocked plating; defectivity reduction; device side-front side; front opening unified pod; high volume manufacturing; line voids; missing pattern; surface defects; wafer cleaning; wafer surface; yield improvement; yield increase; Atmospheric measurements; Contamination; Inspection; Plating; Surface cleaning; Backside; Blocked Plating; Capacity; Clean; Defectivity; Flakes; Improvement; Line Voids; Missing Pattern; Yield;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference (ASMC), 2015 26th Annual SEMI
Conference_Location
Saratoga Springs, NY
Type
conf
DOI
10.1109/ASMC.2015.7164424
Filename
7164424
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