DocumentCode :
725104
Title :
Yield enhancement and mitigating the Si-chipping and wafer cracking in ultra-thin 20µm-thick 8- and 12-inch LSI wafer
Author :
Murugesan, M. ; Fukushima, T. ; Bea, J.C. ; Lee, K.W. ; Koyanagi, M.
Author_Institution :
Global INTegration Initiative (GINTI), Tohoku Univ., Sendai, Japan
fYear :
2015
fDate :
3-6 May 2015
Firstpage :
435
Lastpage :
439
Abstract :
We have meticulously investigated several pre-grinding parameters such as edge trimming width, depth, and edge-back rinse of smeared glue to mitigate the Si chipping and cracking and to enhance the yield in ultra-thin LSI wafer thinning for the thickness value of up to 20 μm, with respect to different types of temporary bonding glue and the glue thickness. After optimizing several pre-grinding and the post-grinding parameters, we found that an intermediate edge-back-rinse process before the final grinding tremendously reduces the Si chipping and wafer cracking, which enhances the yield of ultra-thin wafer grinding.
Keywords :
adhesive bonding; cracks; grinding; integrated circuit yield; large scale integration; semiconductor technology; silicon; Si; bonding glue; edge trimming width; large scale integration; postgrinding parameter; pregrinding parameter; silicon chipping mitigation; size 20 mum; smeared glue edge-back rinse process; ultrathin LSI wafer; ultrathin wafer grinding; wafer cracking; yield enhancement; Bonding; Glass; Image edge detection; Integrated circuits; Silicon; Thermal resistance; Si chipping; Wafer thinning; wafer cracking;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Semiconductor Manufacturing Conference (ASMC), 2015 26th Annual SEMI
Conference_Location :
Saratoga Springs, NY
Type :
conf
DOI :
10.1109/ASMC.2015.7164435
Filename :
7164435
Link To Document :
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