Shortening of cycle time in semiconductor manufacturing via meaningful lot sizes

Cycle time requirements from prime or major customers contradict the ever-increasing complexity of wafer fabrication. Lot size variations show up as significant cycle time improvement potential for single wafer processes. Further reduction potential aside of process times is shown regarding tool-internal waiting times. A model is elaborated to assure cost efficiency while significantly reducing lot raw tool time. The models innovation is to combine real lot move data with inside tool logistics to extend current research activities, including a simulation for its evaluation. Results of raw tool time reduction point to strategies for the surrounding WIP flow control.