High aspect ratio etch yield improvement by a novel polymer dump thickness metrology

Author

Ye, Jeff J. ; Ega, Ganga R. ; Thompson, Shaun P.

Author_Institution

Micron Technol., Inc., Manassas, VA, USA

fYear

2015

fDate

3-6 May 2015

Firstpage

161

Lastpage

166

Abstract

Unexpected yield loss in high-volume DRAM manufacturing occurs very often as an excursion in critical levels such as high aspect ratio container (HARC) etch in capacitor formation in the device. The main failure mode is polymer formation and plasma density change during the chamber preventive maintenance. In this paper we study the effect of polymer formation on HARC profile at various electrostatic chuck (ESC) temperatures and demonstrate a novel and advanced inline metrology - polymer dump thickness measurement - to automatically detect chamber deviation and significantly improve the yield.

Keywords

DRAM chips; capacitors; etching; failure analysis; integrated circuit measurement; integrated circuit yield; plasma density; polymers; preventive maintenance; DRAM manufacturing; ESC temperature; HARC profile; capacitor formation; chamber preventive maintenance; electrostatic chuck; failure mode; high aspect ratio etch yield improvement; inline metrology; plasma density; polymer dump thickness metrology; Containers; Etching; Plasma temperature; Polymers; Random access memory; Temperature measurement; Capacitor; Contact etch; Container; DRAM; HARC; Plasma etch; Polymer; Polymer dump thickness;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference (ASMC), 2015 26th Annual SEMI

Conference_Location

Saratoga Springs, NY

Type

conf

DOI

10.1109/ASMC.2015.7164461

Filename

7164461