A compact I/Q imbalance calibration technique for power-aware fully-integrated receiver without on-chip baseband processor

The in-phase and quadrature (I/Q) calibration has been typically implemented in DSP/MCU to reject image in receive chain. In this work, a compact, fully-integrated calibration technique is proposed without the need of baseband processors, which is very suitable for low-power low-cost wireless applications. By making use of the transmitter (TX) phase loop lock (PLL) in frequency duplex division (FDD) mode, a clean, compact calibration source is implemented with only 0.069mm² extra area. The proposed calibration technique has been applied to an FDD transceiver in 0.13-μm CMOS technology. The measurements show that with the proposed calibration, a -60-dBc image rejection ratio (IRR), a minimum 1.7% error vector magnitude (EVM), and a 26-μs calibration time are achieved.1