8GSps 6bit DAC in 0.18um SiGe technology

Author

Li Wei-zhong ; Zhou Lei ; Xue Dao-jun ; Wu Dan-yu ; Jiang Fan ; Wu Jin ; Yang Qi ; Yu Shao-hua

Author_Institution

State Key Lab. of Opt. Commun. Technol. & Networks, Wuhan Res. Inst. of Post & Telecommun., Wuhan, China

fYear

2015

fDate

March 30 2015-April 1 2015

Firstpage

1

Lastpage

4

Abstract

This paper describes the circuit design and measured performance of a 6-bit 8-GS/s current-steering DAC. A CML interface supporting the maximum conversion rate of 8Gbps is integrated in the chip. A PRBS-7 generator is built in the chip for synchronization as well as for data descrambling. In order to realize good linearity performance, a 2-2-2 segmental architecture is proposed for optimizing the performance. Measured DNL and INL are within +0.04/-0.12 LSB and +0.11/-0.11 LSB respectively. SFDR is above 37dBc over the Nyquist bandwidth at the sampling rate of 8 GS/s. The chip measures 1420 ×1405 um².

Keywords

BiCMOS integrated circuits; current-mode logic; digital-analogue conversion; random number generation; 2-2-2 segmental architecture; CML interface; Nyquist bandwidth; PRBS-7 generator; SiGe; SiGe technology; circuit design; current-steering DAC; digital-to-analog converters; size 0.18 mum; word length 6 bit; Delays; Generators; Linearity; Semiconductor device measurement; Silicon germanium; Synchronization; DAC; I/O; high linearity; high speed;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Symposium (IWS), 2015 IEEE International

Conference_Location

Shenzhen

Type

conf

DOI

10.1109/IEEE-IWS.2015.7164589

Filename

7164589