Area and routing efficiency of SWD circuits compared to advanced CMOS

Author

Zografos, Odysseas ; Raghavan, Praveen ; Sherazi, Yasser ; Vaysset, Adrien ; Ciubatoru, Florin ; Soree, Bart ; Lauwereins, Rudy ; Radu, Iuliana ; Thean, Aaron

Author_Institution

imec, Leuven, Belgium

fYear

2015

fDate

1-3 June 2015

Firstpage

1

Lastpage

4

Abstract

In this paper, we present a standard cell design methodology for Spin Wave Device (SWD) circuits. We perform Place and Route (P&R) experiments against a 10nm FinFET CMOS technology and compare the area, the routing and metal distribution of several arithmetic benchmarks. We show that SWD circuits although they require more metal layers than CMOS designs and although they contain double the number of nets, their pin density and net length distribution makes them easier (2× shorter nets) and cheaper (13% less wiring required) to route than CMOS, without impact the area of the designs.

Keywords

CMOS integrated circuits; MOSFET circuits; integrated circuit design; network routing; spin waves; CMOS designs; FinFET CMOS technology; P&R experiments; SWD circuits; cell design methodology; metal distribution; metal layers; net length distribution; pin density; place and route experiments; routing efficiency; size 10 nm; spin wave device; Benchmark testing; CMOS integrated circuits; Logic gates; Magnetization; Metals; Routing; Standards;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2015 International Conference on

Conference_Location

Leuven

Type

conf

DOI

10.1109/ICICDT.2015.7165881

Filename

7165881