Dimensioning for power and performance under 10nm: The limits of FinFETs scaling

In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. The device parasitics appear as most important performance limiters. Following a top-down approach, we find the design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and a design level solution consisting in fin depopulation. The efficiency of each solution depends on the balance between interconnect and device parasitics.