• DocumentCode
    725697
  • Title

    Simple technique for prediction of breakdown voltage of ultrathin gate insulator under ESD testing

  • Author

    Mitani, Yuichiro ; Matsuzawa, Kazuya

  • Author_Institution
    Adv. LSI Res. Lab., Toshiba Corp., Kawasaki, Japan
  • fYear
    2015
  • fDate
    1-3 June 2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this study, simple ramped voltage TLP (RV-TLP) measurement was utilized to predict breakdown voltage (BVOX) and number of pulses to breakdown (NBD) under ESD testing. The proposed prediction method does not require lengthy DC-TDDB measurements but instead utilizes quick Ramped Voltage (RV) stress measurements to calculate a voltage to breakdown (BVOX) in the ESD timeframe. From voltage ramping rate dependence of QBD and breakdown current (JBD), the power law between QBD and JBD was obtained. By using this QBD-JBD correlation, we succeeded the predictions of BVOX and NBD analytically, and these values correspond to that for conventional constant-voltage TLP measurement. Furthermore, according to the evaluation of QP, anode-hole-injection (AHI) model is still adaptable for the breakdown under nanosecond pulse ESD testing.
  • Keywords
    ULSI; electrostatic discharge; insulators; semiconductor device breakdown; ESD testing; QBD; anode-hole-injection model; breakdown current; breakdown voltage; power law; ramped voltage TLP measurement; ramped voltage stress measurements; ultrathin gate insulator; voltage ramping rate dependence; Current measurement; Electrostatic discharges; Logic gates; Stress; Transmission line measurements; Voltage measurement; Anode-hole-injection model; Breakdown voltage; ESD; SiON; TLP;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    IC Design & Technology (ICICDT), 2015 International Conference on
  • Conference_Location
    Leuven
  • Type

    conf

  • DOI
    10.1109/ICICDT.2015.7165892
  • Filename
    7165892