Impact of device and interconnect process variability on clock distribution

For sub-28nm, process variations became more important. Clock distribution networks are sensitive to those variations because they lead to increased clock skew, which translates to a deterioration of the performance. In this scope, it is the first time that different existing processes are compared. We consider self-aligned double patterning (SADP) and triple expose triple etch (LELELE). First we study the sensitivity of clock skew to interconnect capacitance and resistance. Next we present the influence of the geometry of the tree as the chip size and the clock tree depth. We also investigate the performance of adding air gaps between wires. The results show that the skew is more sensitive to the variation of resistance of the lower metal layers (Mx) and of capacitance of the upper metal layers (Mz). Thus we choose triple-expose triple-etching (LELELE) process for Mx and a relaxed metal pitch for Mz in order to optimize RC-variations. By increasing the depth of the tree the front-end of line (FEOL) influence on skew becomes more dominant with respect to the back-end of line (BEOL) as the number of drivers grows up exponentially with respect to the depth. In the end, we find a trade-off between power consumption and skew deviation with the introduction of air gaps between wires. For a reduction of 9% of the capacitance thanks to the air gaps, the power consumption decreases by the same percentage (6%) as the skew deviation.