Preliminary 3D TCAD electro-thermal simulations of BIMOS transistor in thin silicon film for ESD protection in FDSOI UTBB CMOS technology

Author

Athanasiou, S. ; Cristoloveanu, S. ; Galy, Ph

Author_Institution

STMicroelectron., Crolles, France

fYear

2015

fDate

1-3 June 2015

Firstpage

1

Lastpage

4

Abstract

The purpose of this paper is to analyze the ESD device electro-thermal behavior of BIMOS transistors integrated in ultrathin silicon film for 28 nm FDSOI UTBB high-k metal gate technology. This evaluation is based on 3D TCAD simulations with classical physical models using Average Current Slope (ACS) method and quasi-static DC stress (Average Voltage Slope (AVS) method). We show how the series resistance and the thermal resistance impact the average and peak temperatures in these devices.

Keywords

CMOS integrated circuits; MOSFET; bipolar transistors; electrostatic discharge; 3D TCAD electro-thermal simulations; BIMOS transistor; ESD protection; FDSOI UTBB CMOS technology; average current slope method; average voltage slope method; high-K metal gate technology; quasistatic dc stress; size 28 nm; ultrathin silicon film; BiCMOS integrated circuits; Electrostatic discharges; Mathematical model; Silicon; Stress; Thermal resistance; Transistors; BIMOS transistor; CMOS; ESD protection; FDSOI;

fLanguage

English

Publisher

ieee

Conference_Titel

IC Design & Technology (ICICDT), 2015 International Conference on

Conference_Location

Leuven

Type

conf

DOI

10.1109/ICICDT.2015.7165913

Filename

7165913