Title :
A Sub-1 V Transient-Enhanced Output-Capacitorless LDO Regulator With Push–Pull Composite Power Transistor
Author :
Sau Siong Chong ; Pak Kwong Chan
Author_Institution :
Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
Abstract :
An output-capacitorless low-dropout (OCL-LDO) regulator with a push-pull composite power transistor is presented in this paper. Using the proposed composite transistor, the nondominant parasitic poles can be pushed to higher frequencies, leading to good stability. In addition, the slew rate limitation at the gate of the power transistor is improved greatly by the proposed push-pull structure. Implemented and fabricated in UMC 65-nm CMOS technology, the LDO regulator occupies only an active area of 0.0096 mm2. The experimental results have shown that the regulator is able to operate at VIN = 0.75 V and deliver a maximum load current of 50 mA with a dropout voltage of less than 250 mV. It consumes a quiescent current of 16.2 μA and is able to settle within 1.2 μs.
Keywords :
CMOS integrated circuits; circuit stability; composite materials; power MOSFET; power integrated circuits; OCL-LDO regulator; UMC CMOS technology; current 16.2 muA; current 50 mA; nondominant parasitic pole; push-pull composite power transistor; size 65 nm; slew rate limitation; stability; time 1.2 mus; transient-enhanced output-capacitorless low-dropout regulator; voltage 0.75 V; voltage 1 V; Capacitors; Logic gates; Power transistors; Regulators; Stability analysis; Transistors; Voltage control; Composite power transistor; low-dropout (LDO) voltage regulator; low-voltage regulator; output-capacitorless (OCL) LDO regulator; push-pull.; push??pull;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2013.2290702