Petri Nets-based design of real-time reconfigurable networks on chips

This paper is interested in the run-time adaptation of reconfigurable Multiprocessor System on Chip MPSoC architectures to their environment. A reconfiguration consists in the addition, removal or update of OS tasks to be executed in the different processors under real-time constraints. These tasks are with precedence constraints and exchange messages on the Network on Chip NoC that links different processors. Nevertheless, the intensive application of reconfigurations increases the frequency of the exchanged messages which become more and more important. The saturation problem of routers is then possible. We aim to prove by this research that all reconfigurable messages reach their target destinations and also respect their time constraints. Thus, the need to explore several paths instead of a faulty one is recommended. We propose a routing algorithm that allows a feasible real-time NoC after any reconfiguration scenario. This algorithm is split into two steps where the former deals with the look for minimal possible paths and the latter deals with a selected path that the messages will follow. This contribution is applied to a case study that we model by the formalism Reconfigurable Timed Net Condition Event System R-TNCES to verify temporal logic properties with the model Checker SESA.