Robust low power dual-mode GNSS receiver in 65-nm CMOS for multi-radio SoC integration

This paper presents a highly integrated Global Navigation Satellite System (GNSS) receiver supporting dual-mode GPS and GLONASS operation. The presented GNSS module is co-integrated on a single System on Chip (SoC) with cellular and connectivity transceivers and power management module. Therefore, the receiver is designed to sustain stringent co-existence requirements to cohabit with other on-chip RF modules. This is achieved thanks to chip-package-board co-design, co-simulation and co-optimization methodology and by several system architecture techniques. Chip area is reduced by embedding source-degeneration inductor of the low noise amplifier (LNA) in the fan-out area of the package. The SoC is realized in a standard 65 nm digital CMOS technology. Measured receiver gain is 105 dB and 99 dB for GPS and GLONASS paths, respectively. Measured NF is 1.8 dB, 1dB desensitization for 1710 MHz blocker is -22 dBm.