A 9.8 Gbps, 6.5 mW forwarded-clock receiver with phase interpolator and equalized current sampler in 65 nm CMOS

Author

Shunli Ma ; Manoj, Sai ; Hao Yu ; Junyan Ren ; Weerasekera, Roshan

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2015

fDate

17-22 May 2015

Firstpage

1

Lastpage

4

Abstract

A full-rate energy-efficient forwarded-clock (FC) receiver is demonstrated in this paper. A current sampler with continuous-time equalization is realized with 20 GHz bandwidth in sampling for data recovery. Moreover, a phase interpolator is introduced to generate sampling clock with deskew for data recovery. The testing chip was fabricated in 65 nm CMOS process in area of 0.16 mm². Measurement shows that the FC receiver can achieve a data-rate up to 9.8 Gbps and power consumption is 6.5 mW.

Keywords

CMOS integrated circuits; clocks; equalisers; injection locked oscillators; low-power electronics; CMOS process; FC receiver; bandwidth 20 GHz; continuous-time equalization; current sampler; data recovery deskew; energy-efficient forwarded-clock receiver; phase interpolator; power 6.5 mW; size 0.16 mm; size 65 nm; CMOS integrated circuits; CMOS technology; Clocks; Large scale integration; Oscillators; Receivers; Forwarded-clock receiver; current-sampling; phase interpolator;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium (IMS), 2015 IEEE MTT-S International

Conference_Location

Phoenix, AZ

Type

conf

DOI

10.1109/MWSYM.2015.7166838

Filename

7166838