A 60GHz digitally-assisted power amplifier with 17.2dBm Psat, 11.3% PAE in 65nm CMOS

Author

Yuan Liang ; Nan Li ; Fei Wei ; Yu Hao ; Xiuping Li ; Junfeng Zhao ; Wei Yang ; Yuangang Wang

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore

fYear

2015

fDate

17-22 May 2015

Firstpage

1

Lastpage

4

Abstract

A digitally-assisted CMOS 60GHz PA is reported with high output power and improved power efficiency during power back-off. To combine large number of CMOS power transistors within compact area, a 2D distributed in-phase power combiner is utilized. Moreover, digitally-assisted self-tuning biasing is introduced for power back-off efficiency improvement, where DC power is reduced along with output power. One digitally-assisted 4-way power-combined PA prototype was implemented in 65nm CMOS process with measured output power of 17.2dBm, PAE of 11.3%, and up to 170~190% efficiency improvement during power back-off for the entire 7GHz band at 60GHz.

Keywords

CMOS analogue integrated circuits; low-power electronics; millimetre wave amplifiers; power amplifiers; power combiners; power transistors; 2D distributed in-phase power combiner; CMOS power transistors; CMOS process; DC power; bandwidth 7 GHz; digitally-assisted 4-way power-combined PA; digitally-assisted CMOS PA; digitally-assisted power amplifier; digitally-assisted self-tuning biasing; frequency 60 GHz; power back-off efficiency improvement; power efficiency; size 65 nm; CMOS integrated circuits; Lead;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium (IMS), 2015 IEEE MTT-S International

Conference_Location

Phoenix, AZ

Type

conf

DOI

10.1109/MWSYM.2015.7166918

Filename

7166918