A new compact high-efficiency mmWave power amplifier in 65 nm CMOS process

Author

Tianzuo Xi ; Huang, Sherry ; Guo, Shita ; Ping Gui ; Jing Zhang ; Wooyeol Choi ; Daquan Huang ; Kenneth, K.O. ; Fan, Yanli

Author_Institution

Dept. of Electr. Eng., Southern Methodist Univ., Dallas, TX, USA

fYear

2015

fDate

17-22 May 2015

Firstpage

1

Lastpage

4

Abstract

This paper presents a new design technique for high-efficiency CMOS mmWave power amplifier (PA). The proposed PA adopts NMOS capacitors connected at the gates of the transistors of the last amplifying stage to compensate gate capacitance variation over large signal swing, improving the linearity and the power efficiency. Implemented in 65 nm CMOS process, the presented PA consists of two differential stages, uses baluns, transformers and inductors to realize the input, output, and inter-stage power matching, and achieves a peak PAE of 24.2%, a 6 dB back-off PAE of 10.5% from 3 dB gain compression, a maximum gain of 17 dB, and a 3-dB bandwidth from 68 to 78 GHz.

Keywords

CMOS analogue integrated circuits; MOS capacitors; baluns; inductors; integrated circuit design; millimetre wave power amplifiers; transformers; CMOS process; NMOS capacitors; compact high-efficiency mmWave power amplifier; gain compression; gate capacitance variation; high-efficiency CMOS mmWave power amplifier; interstage power matching; power efficiency; signal swing; size 65 nm; CMOS integrated circuits; CMOS technology; Capacitance; Capacitors; Logic gates; MOS devices; Tracking loops; NMOS capacitors; Power amplifier (PA); capacitance linearization; high efficiency; mmWave;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Symposium (IMS), 2015 IEEE MTT-S International

Conference_Location

Phoenix, AZ

Type

conf

DOI

10.1109/MWSYM.2015.7167051

Filename

7167051