DocumentCode :
726401
Title :
OSFA: A new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions
Author :
Roy, Subhendu ; Derong Liu ; Junhyung Um ; Pan, David Z.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA
fYear :
2015
fDate :
8-12 June 2015
Firstpage :
1
Lastpage :
6
Abstract :
Modern SoCs and microprocessors, e.g., those in smart phones and laptops, typically have multiple operating conditions, such as video streaming, web browsing, standby, and so on. They will have different performance targets and run under different supply voltages. Gate sizing (with threshold voltage assignment) is a fundamental step for power/performance optimization. However, conventional gate sizing algorithms only consider one scenario, e.g., the performance-critical operating condition, which may be over-design for other operating conditions. In this paper, we present a new paradigm of gate sizing, OSFA (One-Size-Fits-All), which performs power/performance optimizations across multiple operating conditions. Based on OSFA, we also adjust the supply voltage targeting overall power optimization. Experimental results on industry-strength benchmarks demonstrate that compared with conventional approach OSFA could provide an average 6.1% reduction in power without performance loss.
Keywords :
microprocessor chips; power aware computing; system-on-chip; OSFA paradigm; SoC; gate sizing algorithms; gate-sizing paradigm; microprocessors; one-size-fits-all paradigm; performance targets; performance-critical operating condition; power-performance optimization; supply voltages; system-on-chip; threshold voltage assignment; Delays; Libraries; Logic gates; Optimization; Sensitivity; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
Type :
conf
DOI :
10.1145/2744769.2744885
Filename :
7167314
Link To Document :
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