DocumentCode :
726410
Title :
A lightweight early arbitration method for low-latency asynchronous 2D-mesh NoC´s
Author :
Weiwei Jiang ; Bhardwaj, Kshitij ; Lacourba, Geoffray ; Nowick, Steven M.
Author_Institution :
Dept. of Comput. Sci., Columbia Univ., New York, NY, USA
fYear :
2015
fDate :
8-12 June 2015
Firstpage :
1
Lastpage :
6
Abstract :
A new asynchronous low-latency interconnection network is introduced for a 2D mesh topology. The network-on-chip, named AEoLiAN, contains a fast lightweight monitoring network to notify the routers of incoming traffic, thereby allowing arbitration and channel allocation to be initiated in advance. In contrast, several recent synchronous early arbitration methods require significant resource overhead, including use of hybrid networks, or wide monitoring channels and additional VCs. The proposed approach has much smaller overhead, allowing a finer-grain router-by-router early arbitration, with monitoring and data advancing independently at different speeds. The new router was implemented in 45nm technology using a standard cell library. It had 52% lower area than a similar lightweight synchronous switch, xpipesLite, with no early arbitration capability. Network-level simulations were then performed on 6 diverse synthetic benchmarks in an 8×8 2D mesh network topology, and the performance of the new network was compared to an asynchronous baseline. Considerable improvements in system latency over all benchmarks for moderate traffic were obtained, ranging from 34.4-37.9%. Interestingly, the proposed acceleration technique also enabled throughput gains, ranging from 14.7-27.1% for the top 5 benchmarks. In addition, a zero-load end-to-end latency of only 4.9ns was observed, for the longest network path through 15 routers and 14 hops.
Keywords :
asynchronous circuits; benchmark testing; channel allocation; integrated circuit interconnections; network topology; network-on-chip; switches; 2D mesh topology; 8x8 2D mesh network topology; AEoLiAN; asynchronous low-latency interconnection network; channel allocation; channel monitoring; finer-grain router-by-router early arbitration; lightweight early arbitration method; lightweight monitoring network; lightweight synchronous switch; low-latency asynchronous 2D-mesh NoC; network-level simulations; network-on-chip; resource overhead; synchronous early arbitration methods; synthetic benchmarks; system latency; xpipesLite; zero-load end-to-end latency; Acceleration; Monitoring; Ports (Computers); Routing; Routing protocols; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
Type :
conf
DOI :
10.1145/2744769.2744777
Filename :
7167323
Link To Document :
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