• DocumentCode
    726437
  • Title

    An efficient algorithm for statistical timing yield optimization

  • Author

    Ramprasath, S. ; Vasudevan, V.

  • Author_Institution
    Dept. of Electr. Eng., IIT Madras, Chennai, India
  • fYear
    2015
  • fDate
    8-12 June 2015
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    Statistical timing yield optimization algorithms require computation of yield-gradient for gate resizing in every iteration. Numerical yield-gradients account for the effects of fan-in and fan-out gates, but are computationally expensive. In this paper, we formulate a more accurate analytical expression for the yield-gradient (termed effective yield-gradient) that includes these effects. Based on the statistical properties of the path delay variations, we derive a simplified expression for the effective yield gradient that is accurate and results in an improvement in the run-time. Using these simplified expressions, we also propose an algorithm for resizing multiple gates in an iteration. Results on ITC99 and ISCAS85 benchmarks show that the proposed multi-node resizing algorithm results in 83% improvement in the runtime with an average area penalty of 3% and no cost to the final yield achieved.
  • Keywords
    circuit optimisation; integrated circuit yield; statistical analysis; ISCAS85; ITC99; effective yield-gradient; fan-in gate; fan-out gate; multiple gate; path delay variation; statistical property; statistical timing yield optimization algorithm; Approximation methods; Benchmark testing; Delays; Libraries; Logic gates; Optimization; Gate sizing; Timing Yield; Yield Optimization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2015 52nd ACM/EDAC/IEEE
  • Conference_Location
    San Francisco, CA
  • Type

    conf

  • DOI
    10.1145/2744769.2744796
  • Filename
    7167352