Drain-side discrete-distributed layout influences on reliability issues in the 0.25 μm 60-V power pLDMOS

Repercussions on the reliability capability and electrical performance of power p-channel LDMOS devices by different discrete-distributed architectures in the drainside are investigated in this paper. Here, in order to effectively improve the reliability issues, a drain-side "NPN" and "PNP" styles of pLDMOS-SCR with some discrete-distributed areas arrangement are fabricated by a 0.25 μm 60 V BCD process. From the experimental results, we can find that the layout manner of discrete-distributed types in the drain-side have little impacts on the anti-ESD capability, due to their secondary breakdown current (I_t2) values are greater than 7 A. On the other hand, the lowest N⁺/P⁺ area ratio of discrete-distributed type has a better electrical property and anti-latchup (LU) immunity than that of the reference DUT (type-6). In other words, the layout type of "NPN_discrete 3_2co" has a higher V_t1, V_h, and V_BK values; the V_t1 improvement is more than 18.2%, V_h improvement is more than 25.6%, and V_BK improvement is more than 24.24% as compared with the reference DUT (type-6), respectively. Finally, it can be summarized that the "PNP" stripe-type (type 7) is the best choice for the anti-ESD/LU immunities and electrical performance considerations.