Gate driving method for synchronous rectifiers in phase-shifted full-bridge converter

In high output current applications such as server power system, a phase-shifted full-bridge (PSFB) converter uses parallel connected power MOSFETs in synchronous rectifiers to reduce secondary conduction loss. However, it causes large gate driving loss. Therefore, this paper proposes a simple synchronous rectifiers (SRs) gate driving method for the PSFB converter. The proposed method reduces the supply voltage of SRs gate driver with a conventional input resistor and capacitor of SRs gate driver during the overlapping time of OR-gated signals in SRs. Therefore, without additional components and control techniques, the proposed method can significantly reduce the gate driving loss on SRs especially in light load conditions. The validity of the proposed method is confirmed by experimental results from a prototype with 400V input and 750W/12V output.