Title :
System clock reduction based on multiple sampling for digital switching power supplies
Author :
Yau, Y.T. ; Hwu, K.I. ; Jiang, W.Z.
Author_Institution :
Dept. of Electr. Eng., Nat. Taipei Univ. of Technol., Taipei, Taiwan
Abstract :
In this paper, the proposed sampling structure based on one-comparator sampling is presented, which can significantly reduce the system clock frequency from 100MHz to 25MHz, so as to reduce chip area. This method is verified by a synchronously-rectified buck converter with a switching frequency of 200kHz, and the digital controller takes as a control kernel the EP1C3T100 FPGA created by Altera Co., along with the VHDL language to program this controller.
Keywords :
comparators (circuits); digital control; field programmable gate arrays; hardware description languages; power convertors; switched mode power supplies; EP1C3T100 FPGA; VHDL language; chip area; control kernel; digital controller; digital switching power supplies; frequency 100 MHz; frequency 200 kHz; frequency 25 MHz; one-comparator sampling; sampling structure; synchronously-rectified buck converter; system clock frequency; Capacitors; Clocks; Control systems; Field programmable gate arrays; Pulse width modulation; Sampling methods; Voltage control; ADC; FPGA; PWM; system clock;
Conference_Titel :
Power Electronics and ECCE Asia (ICPE-ECCE Asia), 2015 9th International Conference on
Conference_Location :
Seoul
DOI :
10.1109/ICPE.2015.7168192
