A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter

In this paper, a fourth-order ΔΣ time-to-digital converter (TDC) is proposed to achieve high resolution and wide signal bandwidth. The proposed TDC is based on a 1-3 multi-stage-noise-shaping (MASH) architecture, where the first-stage is a gated-ring oscillator based TDC (GRO-TDC) and the second-stage is a single-loop third-order ΔΣ TDC based on a time-domain error-feedback filter using time registers, time adders and time amplifiers. Implemented in 65 nm CMOS process, the prototype TDC achieves 0.22 ps_rms of integrated noise within 15 MHz signal bandwidth at 300 MS/s while consuming lower than 6.24 mW. The proposed TDC occupies an active die area of only 0.03 mm².