DocumentCode
726939
Title
A secure design-for-test infrastructure for lifetime security of SoCs
Author
Backer, Jerry ; Ali, Sk Subidh ; Rosenfeld, Kurt ; Hely, David ; Sinanoglu, Ozgur ; Karri, Ramesh
Author_Institution
Polytech. Sch. of Eng., New York Univ., New York, NY, USA
fYear
2015
fDate
24-27 May 2015
Firstpage
37
Lastpage
40
Abstract
Modular design of a system-on-chip (SoC) exposes intellectual property (IP) and SoC assets to attacks in test, debug, and functional modes. We enhance the SoC Design-for-Test (DfT) infrastructure with security countermeasures to thwart these attacks. We first secure IP and SoC assets from attacks in test and debug modes, then reuse the DfT infrastructure to detect attacks in functional mode.
Keywords
design for testability; industrial property; security of data; system-on-chip; DfT infrastructure; IP assets; SoC assets; debug modes; design-for-test infrastructure; functional modes; intellectual property; lifetime security; modular design; security countermeasures; system-on-chip; test modes; Ciphers; Engines; IP networks; Monitoring; Registers; System-on-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location
Lisbon
Type
conf
DOI
10.1109/ISCAS.2015.7168564
Filename
7168564
Link To Document