Approaches to mitigating the impact of DAC mismatch on the performance of continuous-time delta-sigma modulators

In this paper, two approaches to mitigating the impact of DAC mismatch on the performance of continuous-time Delta-Sigma modulators are presented. The first approach equals an optimized analog calibration which provides better robustness to disturbances of the calibration signal. The second approach, a new dynamic element matching technique labeled clock frequency modulation, modulates mismatch dependent inband distortion of a multi-bit DAC to out-of-band. Due to its simplicity, it is well suited for application in high-speed designs. Simulations performed on transistor-level implementations of the DACs embedded in a Verilog-A model based third-order continuous-time Delta-Sigma modulator prove the feasibility of the approaches.