DocumentCode
727010
Title
Multi-phase bang-bang digital phase lock loop with accelerated frequency acquisition
Author
Samarah, Amer ; Carusone, Anthony Chan
Author_Institution
Edward S. Rogers Sr. Dept. of Electr. & Comput. Eng., Univ. of Toronto, Toronto, ON, Canada
fYear
2015
fDate
24-27 May 2015
Firstpage
545
Lastpage
548
Abstract
A highly digital phase lock loop with a multi-phase bang-bang phase detector is proposed to speed up lock time and to increase the pull in range. To reduce power consumption, the high speed counter and re-timing circuit in the feedback loop are disabled after frequency lock is achieved.
Keywords
circuit feedback; digital phase locked loops; phase detectors; accelerated frequency acquisition; digital phase lock loop; feedback loop; frequency lock; high speed counter; lock time; multi-phase bang-bang phase detector; power consumption; pull in range; re-timing circuit; Clocks; Detectors; Frequency locked loops; Phase locked loops; Phase noise; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2015 IEEE International Symposium on
Conference_Location
Lisbon
Type
conf
DOI
10.1109/ISCAS.2015.7168691
Filename
7168691
Link To Document