Area efficient configurable physical unclonable functions for FPGAs identification

Physical Unclonable Functions (PUF) is an emerging design technology for secure hardware. It exploits the physical manufacturing variations of silicon ICs to generate a unique signature for each chip. A Ring Oscillator (RO) based PUF is a promising solution for the authentication of FPGA devices. However; this technique has not yet been widely adopted due to its large area costs and the lack of platform-independent PUF architectures which are “easy to implement”. Existing RO PUF design requires large number of ring oscillators to generate a relatively safe unique identifier; they also have complex routing requirements. This work proposes a novel configurable RO PUF architecture easily portable between different FPGA platforms. It also offers significantly larger number of challenge-response pairs compared to existing solutions with the same area overheads. The design was realized and characterized using an Altera FPGA device. Experimental results show that the quality of this design conforms to the requirements of general RO PUF.