Design and techniques for on-die power integrity noise measurement system with digital output

In this paper, the authors propose an on-die power supply noise measurement system for power integrity characterization using one bias supply. The measurement system is operated by the bias voltage provided to logical blocks such as Core and IO block in a microprocessor since another supply power rail for the measurement system can create a coupling to the existed power rails. The power supply noise is repetitive since it is created by repetitive on chip circuit activities. The voltage range that can be measured by the system is ±25% of VCC; (including noise which exceeds the power supply voltage) and the range of the noise measurement frequency is up to 1.5GHz. The proposed measurement system is composed of two main sections; one is a sampling and detection system and the other is an effective ADC. In addition, the proposed system is designed in 90nm CMOS technology and is specified to be interacted with system support such as software for a trigger signal and JTAG.