Practical considerations in VLSI IC design flow with respect to tool limitations

Despite great advances in technology, and design and verification tools, it is still impossible to create fully automated IC design flow that would produce working SoC designs with minimal human intervention. Instead, IC are designed and verified by using myriad of (often) non-compatible tools and design flows that are manually interrupted and adapted at will. In this paper some of the practical flow limitations and workarounds are pointed out as an illustration of the state of the art.