Dynamic nets-to-TSVs assignment in 3D floorplanning

We propose a new scheme of dynamic nets-to-TSVs assignment during floorplanning for 3D-ICs. A nontrivial area occupied by TSVs, their physical dimensions, location on the layout and the nets-to-TSVs assignment, are some of the key factors influencing the wirelength, TSV count and chip area, and consequently, impact the total delay. We address the above issues by simultaneous placement of TSV islands with circuit blocks, assignment of nets to TSV islands during floorplanning and directly optimizing interconnect delay. TSVs induce significant thermo-mechanical stress in nearby silicon, and to reduce the impact of stress, we incorporate pitch and Keep-Out-Zone (KOZ) around TSVs in our approach. The proposed dynamic nets-to-TSVs assignment approach, improves solution compared to a previously used fixed nets-to-TSVs assignment, by achieving on average 6-9% delay reduction. Analysis for various TSV aspect ratios using the proposed assignment method is also presented.