Performance evaluation of hierarchical NoC topologies for stacked 3D ICs

Author

Matos, Debora ; Prass, Max ; Kreutz, Marcio ; Carro, Luigi ; Susin, Altamiro

Author_Institution

UERGS - Univ. Estadual do Rio Grande do Sul, Rio Grande, Brazil

fYear

2015

fDate

24-27 May 2015

Firstpage

1961

Lastpage

1964

Abstract

Three-Dimensional (3D) integrated circuits (ICs) have emerged as a solution to attend the demand of high performance, low power and high density of the MultiProcessors Systems-on-Chip (MPSoCs). However, some important issues need to be observed in the interconnection device for 3D designs. In this paper we have presented the advantages of the 3D-HiCIT network-on-chip (NoC) when compared to other hierarchical topologies in terms of flexibility, scalability and performance. Considering all constraints of this new scenario of circuit integration, the proposed hierarchical 3D NoC verified in this work meets well with the reality of these designs, presenting gains in several aspects.

Keywords

multiprocessor interconnection networks; network-on-chip; three-dimensional integrated circuits; 3D-HiCIT network-on-chip; MPSoC; hierarchical NoC topology; interconnection device; multiprocessors systems-on-chip; stacked 3D IC; three-dimensional integrated circuits; Integrated circuit interconnections; Network topology; Proposals; Three-dimensional displays; Through-silicon vias; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2015 IEEE International Symposium on

Conference_Location

Lisbon

Type

conf

DOI

10.1109/ISCAS.2015.7169058

Filename

7169058