Gain enhanced high frequency OTA with on-chip tuned negative conductance load

Author

Mondal, Imon ; Krishnapura, Nagendra

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol. Madras, Chennai, India

fYear

2015

fDate

24-27 May 2015

Firstpage

2085

Lastpage

2088

Abstract

An enhanced gain, high frequency, operational transconductance amplifier (OTA) architecture using negative conductance load to cancel its output parasitic conductance across process, voltage, and temperature (PVT) variations without the need of any off-chip intervention is proposed. Simulation results of a prototype transconductor in 0.13μm CMOS process over process corners, 100°C temperature range, and ±10% supply voltage variations show that the DC gain is enhanced from 14dB to 48dB when cancellation using negative conductance is incorporated. A minimum DC gain of 34dB and an average DC gain of 46dB is observed over 500 Monte-Carlo mismatch runs. The OTA has a unity gain bandwidth (UGB) of 20GHz.

Keywords

CMOS integrated circuits; Monte Carlo methods; circuit tuning; electric admittance; operational amplifiers; CMOS process; DC gain; Monte-Carlo mismatch run; PVT variation; UGB; bandwidth 20 GHz; complementary metal oxide semiconductor; gain 14 dB to 48 dB; gain 34 dB; gain enhanced high frequency OTA; off-chip intervention; on-chip tuned negative conductance load; operational transconductance amplifier; parasitic conductance; process voltage and temperature variation; size 0.13 mum; temperature 100 C; unity gain bandwidth; Clocks; Computer architecture; Gain; Logic gates; Transconductance; Transistors; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2015 IEEE International Symposium on

Conference_Location

Lisbon

Type

conf

DOI

10.1109/ISCAS.2015.7169089

Filename

7169089