Fault-aware configurable logic block for reliable reconfigurable FPGAs

Field Programmable Gate Arrays (FPGAs) used in mission-critical applications such as aerospace, nuclear, and defense require high reliability in spite of internal faults. Fortunately, today´s FPGAs have the ability to dynamically reconfigure themselves in the field, which may help to mitigate the effects of certain faults affecting the FPGA devices. Although the reconfiguration process can remove only the upsets affecting the configuration bitstream, unfortunately, there are other sources of faults that might directly affect hardware resources of reconfigurable FPGAs. Their nature and consequences differ from those which occur in the configuration bitstream and their effects cannot be corrected by performing configuration writeback. This paper proposes a fault-aware configurable logic block architecture to detect such faults in FPGA-implemented logic circuits. The fault coverage of the proposed architecture is also discussed. Hardware complexity estimations suggest higher efficiency of the approach proposed over similar existing ones.