• DocumentCode
    728863
  • Title

    Regression Testing of GPU/MIC Systems for HPCC

  • Author

    Reza, Hassan ; Aguilar, Michael ; Jalal, Sara Faraji

  • Author_Institution
    Dept. of Comput. Sci., Univ. of North Dakota, Grand Forks, ND, USA
  • fYear
    2015
  • fDate
    18-18 May 2015
  • Firstpage
    30
  • Lastpage
    37
  • Abstract
    Multicore GPU, Intel MIC, and FPGA supplemental parallel processors have become widely implemented in High Performance Computing Clusters (HPCCs). In HPCCs, Computing nodes are assembled with these supplemental processors for specific research applications, images are applied to do the research. Since HPCC computing nodes require completely different design configuration from one day to the next, System Administrators are being challenged to verify that each of these computing images work correctly, in all needed applications. Due to the large cost in man-hours that are expended with manual testing of each computing node and the entire HPCC system for defects, there is a need for automated regression testing on parallel, distributed, and heterogeneous computing nodes. Existing approaches at automated regression testing deals only with simple homogeneous HPCC topologies. What is needed is a regression testing technique to include heterogeneous HPCC topologies that deal with computing nodes containing supplemental GPUs, Intel MIC cards, FPGAs, etc. This paper presents a case-study to perform regression testing using Equivalence Class Partitioning (ECP) and Boundary Value testing techniques. The method has been employed to test HPCCs configured of heterogeneous computing nodes. More specifically, the computing nodes configured for this experiment include NVidia GPU and Intel MIC Xeon Phi cards deployed in HPCC clusters.
  • Keywords
    field programmable gate arrays; graphics processing units; parallel processing; pattern clustering; regression analysis; ECP; FPGA supplemental parallel processors; Intel MIC Xeon Phi cards; NVidia GPU; automated regression testing; boundary value testing techniques; design configuration; equivalence class partitioning; field programmable gate arrays; graphical processing units; heterogeneous computing nodes; high performance computing clusters; homogeneous HPCC topologies; manual testing; multicore GPU; system administrators; Computational modeling; Field programmable gate arrays; Graphics processing units; Hardware; Microwave integrated circuits; Testing; FPGA; GPU; HPCC; Intel MIC; Petri Nets; Regression Testing; Software Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Software Engineering for High Performance Computing in Science (SE4HPCS), 2015 IEEE/ACM 1st International Workshop on
  • Conference_Location
    Florence
  • Type

    conf

  • DOI
    10.1109/SE4HPCS.2015.12
  • Filename
    7173508