Programming protocol optimization for analog weight tuning in resistive memories

Resistive memories (also called memristors) demonstrate attractive features such as excellent scaling prospects, fast switching speed and high retention. In addition, many resistive memories can tune the conductance continuously by applying voltage pulses consecutively (e.g. positive pulses to gradually increase conductance and negative pulses to gradually decrease conductance). Such conductance modulation capability has attracted significant attention to function as synaptic devices for neuro-inspired computing. Recently, F. Alibart, et al. proposed an adaptable variation-tolerant algorithm to tune TiO_x based resistive devices to an intermediate state by varying pulse widths and amplitudes. However, the programming protocol in F. Alibart´s approach is not optimized, thus it is time consuming to reach the target conductance. In this work, we propose optimization strategies of programming protocols by adjusting the pulse amplitude incremental steps, the pulse width incremental steps, and the start voltages. We performed the experiments on the HfO_x based resistive devices. We identified that the key limiting factor for the tuning convergence speed is the overshoot due to the stochastic nature of the switching dynamics. Therefore, optimizing the incremental steps of voltage carefully to avoid overshoot is critical for fast tuning.