III–V device integration on Si using template-assisted selective epitaxy

High mobility (III-V) materials have long been anticipated to replace Si MOSFETs. But only recently [1] were scaled InAs MOSFETs reported to outperform Si devices. However, high-performing III-V devices are typically fabricated on InP substrates which are not compatible with large-scale chip manufacturing. While various III-V on Si fabrication approaches have been reported to overcome this issue, they either suffer from limited material quality or are economically not competitive compared to Si substrates. Here we demonstrate a versatile approach for heterogeneous integration of III-Vs on Si and validate this by the fabrication of multiple-gate (MuG)-FET devices. The study is complemented by performing TEM analysis, TLM and Hall measurements.