• DocumentCode
    729324
  • Title

    Enhanced Ge n-channel gate stack performance using HfAlO high-k dielectric

  • Author

    Kothari, Shraddha ; Joishi, Chandan ; Biswas, Dipankar ; Vaidya, Dhirendra ; Ganguly, Swaroop ; Lodha, Saurabh

  • Author_Institution
    Dept. of Electr. Eng., IIT Bombay, Mumbai, India
  • fYear
    2015
  • fDate
    21-24 June 2015
  • Firstpage
    285
  • Lastpage
    286
  • Abstract
    Summary form only given. This work reports improved Ge n-channel gate stack performance using HfAlO high-k dielectric versus HfO2. ALD HfAlO high-k results in improved thermal stability for a 400 °C post high-k deposition anneal of gate stacks with thick (8 nm) as well as thin (2 nm) EOT. For thick EOT stacks Al incorporation mainly benefits (10% lower) EOT and interface state density (Dit) whereas for thin EOT stacks the benefits are reduced Jg (10X) and Dit at ~matched EOT. Improvement in gate stack performance for thick EOT stacks is seen even with significantly large Al% (33%) unlike thin EOT stacks where the Al% needs to be kept low to preserve capacitance. In summary, we demonstrate a thermally stable HfAlO gate stack process with tunable Al% for improved performance vs HfO2 over a wide EOT range.
  • Keywords
    annealing; atomic layer deposition; dielectric materials; germanium; hafnium compounds; thermal stability; ALD; EOT stacks; Ge; HfAlO; HfO2; atomic layer deposition; gate stack process; high-k dielectric; interface state density; n-channel gate stack performance; post high-k deposition anneal; size 2 nm; size 8 nm; temperature 400 degC; thermal stability; Annealing; Artificial intelligence; Hafnium oxide; Handheld computers; Logic gates; Reliability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Device Research Conference (DRC), 2015 73rd Annual
  • Conference_Location
    Columbus, OH
  • Print_ISBN
    978-1-4673-8134-5
  • Type

    conf

  • DOI
    10.1109/DRC.2015.7175687
  • Filename
    7175687